Introduction

The rapid proliferation of Internet of Things (IoT) devices—from smart sensors and wearables to industrial monitors—has placed unprecedented demands on integrated circuit design. Most of these devices must operate for months or years on small coin-cell batteries, scavenged energy from ambient sources, or even without any battery at all. This makes power efficiency the single most critical constraint in IoT chip development. Low-power Very Large Scale Integration (VLSI) design techniques are the engineering backbone that enables such extreme energy frugality while still delivering acceptable performance for sensing, processing, and communication.

Without aggressive low-power design, an IoT node that must report sensor data every minute would deplete a typical CR2032 battery in just a few weeks. With modern low-power VLSI methods, the same node can run for over two years. This article explores the most effective low-power VLSI techniques used in IoT devices, the trade-offs engineers must navigate, and the emerging innovations that will push the boundaries even further.

The Power Challenge in IoT Devices

IoT devices are unique in that they spend the vast majority of their time in an idle or sleep state, waking only briefly to collect data, perform minimal processing, and transmit results. This duty cycle is often below 1%. During the active period, the device must still operate at a sufficient speed to handle protocol timings (e.g., Bluetooth Low Energy or Zigbee). The power budget is defined by the battery capacity (e.g., 225 mAh for a CR2032) and the required lifetime (e.g., two years). The average current draw cannot exceed a few microamperes.

Total power consumption in CMOS circuits has two main components: dynamic power (from switching activity) and static (leakage) power (from subthreshold and gate leakage currents). In older process nodes (above 90 nm), dynamic power dominated. As transistor dimensions shrink below 28 nm, leakage power can account for 30% to 50% of the total, especially in always-on blocks. Low-power VLSI design must address both sources.

Key Low-Power VLSI Techniques

Engineers have developed a rich toolbox of design techniques to cut power in IoT chips. The most effective approaches combine architectural choices with circuit-level optimizations. Below are the fundamental techniques, each with its strengths and typical use cases.

1. Power Gating

Power gating is the most direct method to eliminate static power: simply disconnect idle circuit blocks from the supply rail using sleep transistors. A high-threshold voltage (high-Vth) PMOS or NMOS header/footer switch is inserted between the power supply and the logic block. When the block is not needed, the switch is turned off, reducing leakage to near zero. In deep sub-micron nodes, power gating can achieve leakage reductions of 10× to 100×.

However, implementing power gating requires careful management. The block must be state-retentive if it needs to preserve data across sleep periods—often using retention flip-flops with a separate always-on power rail. Wake-up time (the delay to restore the rail voltage and stabilize the logic) must be accounted for. Designers also need to balance the size of the sleep transistors to avoid excessive IR drop during active mode. Many modern IoT SoCs, such as the Ambig Apollo4, use fine-grained power gating to keep only essential always-on domains powered while the rest of the core naps.

2. Dynamic Voltage and Frequency Scaling (DVFS)

Dynamic power is proportional to V2 × f (voltage squared times frequency). By reducing the operating voltage and frequency when the workload is light, dynamic power can be slashed quadratically. DVFS adjusts both together: for a compute-intensive task (e.g., FFT processing), the voltage and frequency are raised; during idle polling, they are lowered to a minimum supported by the logic. This technique is widely used in processors like ARM Cortex-M series, which can scale from 1.8 V down to below 0.9 V in low-leakage operation.

Challenges include the need for an on-chip voltage regulator (typically a low-dropout regulator or a buck converter) that can change voltage quickly, and ensuring that memory cells operate reliably at reduced voltages. Adaptive body biasing can help maintain performance at low VDD. Research shows that combining DVFS with architecture-level parallelism can yield up to 80% energy savings in sensor processing units.

3. Multi-Threshold CMOS (MTCMOS)

MTCMOS uses transistors with different threshold voltages in the same chip. High-Vth transistors have lower leakage but slower switching; low-Vth transistors switch faster but leak more. A typical design uses low-Vth devices on critical timing paths and high-Vth devices everywhere else. This technique was instrumental in the TI CC2652R wireless MCU, which combines a high-performance ARM Cortex-M4F core (low-Vth paths) with a dedicated radio controller and sensor interface built mostly from high-Vth gates to minimize idle leakage.

Modern foundry processes offer multiple Vth options (e.g., SVT, LVT, ULVT). Engineers run static timing analysis to identify paths that need speed and assign the appropriate threshold. The trade-off: more mask layers increase manufacturing cost, but for high-volume IoT chips, the power savings justify the expense.

4. Clock Gating

Clock distribution accounts for a large fraction of dynamic power—often 30% to 40% in a typical SoC. Clock gating disables the clock to any register bank or logic block that does not need to change state. This stops the toggling of flip-flops and combinational cells in the gated domain, reducing dynamic power proportionally to the activity factor.

Standard-cell libraries include integrated clock-gating cells (ICGs) that combine a latch and an AND gate. Synthesis tools automatically insert these on registers with enable signals. For IoT chips, fine-grained clock gating at the RTL level can reduce power by 15–25% at the system level. Additionally, clock-tree gating (cutting off an entire subtree) is used for peripherals like UART or I2C that are inactive for long periods. The Nordic nRF5340 uses aggressive clock gating to achieve sub-1 µA sleep current while keeping the radio ready to listen.

5. Sub-threshold and Near-threshold Design

For the lowest possible power, circuits can be operated in the sub-threshold region—with supply voltage VDD below the transistor threshold voltage Vth. Currents are exponential with voltage, so sub-threshold operation can reduce power by orders of magnitude compared to super-threshold. However, speed drops dramatically (MHz to kHz range) and sensitivity to process variation increases. This technique is best suited for ultra-low-frequency applications like temperature sensors, heart-rate monitors, and wake-up radios that only need kHz clock rates.

A famous example is the MIThril wearable chip, which ran a simple pattern-matching algorithm at 500 kHz consuming only 20 µW. More recently, near-threshold computing (VDD ~0.5 V) has been adopted in some sub-mW IoT processors, such as the GreenWaves GAP8, which operates down to 0.6 V while still delivering 100+ MOPS for AI inference.

6. Energy Harvesting and Adaptive Power Management

Beyond circuit techniques, system-level power management is essential. IoT devices increasingly integrate energy harvesting modules (solar, thermal, RF, vibration) with adaptive algorithms that adjust operation to available energy. For example, a solar-powered environmental sensor might increase sampling rate on sunny days and go into deep sleep during overcast periods. VLSI designers build in on-chip power management units (PMUs) that monitor battery voltage and harvested energy, then coordinate DVFS, power gating, and clock scaling.

The TI BQ25570 is a dedicated PMIC that features ultra-low-power boost charging and programmable power-gating control. Integrating such PMUs on the same die with the digital logic (a power management integrated circuit or PMIC-on-chip) is an emerging trend in advanced IoT nodes.

Design Challenges and Trade-offs

Applying low-power techniques is rarely straightforward. Every method introduces a cost—in area, performance, design complexity, or manufacturing yield. Below are the most significant trade-offs engineers face.

Timing Closure Under Voltage Scaling

DVFS and sub-threshold operation create wide variation in gate delays. A path that meets timing at 1.2 V may fail at 0.8 V. Designers must use static timing analysis across corners (PVT: process, voltage, temperature) and sometimes add adaptive body bias to compensate. This increases design effort by 20–40% compared to a fixed-voltage flow.

Leakage vs. Wakeup Energy

Aggressive power gating saves leakage but consumes energy to wake up: charging the virtual power rail, restoring state, and re-establishing an in-rush current. If the idle period is too short, the wake-up energy may outweigh the leakage saved. A common rule of thumb is to only gate blocks that will be idle for >10× the break-even time. For always-on logic (e.g., a real-time clock), gating is counterproductive.

Process Variation and Reliability

At advanced nodes (7 nm, 5 nm), transistors exhibit significant random doping fluctuations and line-edge roughness. Sub-threshold circuits are especially sensitive—one weak transistor can cause a logic gate to fail. Redundant logic, Schmitt triggers, or robust memory cells (like 10T SRAM) can improve yield at the cost of area. This trade-off is particularly acute for IoT chips that must be extremely low-cost.

Analog and Mixed-Signal Integration

Many IoT devices include RF transceivers, ADCs, and sensors on the same die. While digital logic can be aggressively power-gated and scaled, analog blocks require stable biasing and large devices for matching. They cannot easily be turned off or have their voltage dropped. This forces a split-rail architecture: the analog domain runs at a fixed higher voltage while the digital domain is minimized. The interface between them (level shifters, isolation cells) adds overhead.

The low-power VLSI field continues to evolve rapidly, driven by the insatiable appetite of IoT and edge AI. Several developments promise to further reduce energy consumption while enabling new capabilities.

Machine Learning–Aided Power Management

ML algorithms can learn the workload patterns of a device and predict future idle and active periods. For example, a neural network on the PMU can decide when to enter deep sleep or ramp up voltage, achieving an additional 10–30% power savings over rule-based governors. Companies like Synopsys offer design tools that use ML to optimize power gating and clock gating during synthesis.

New Transistor Architectures: FinFET, GAA, and Beyond

FinFETs (already mainstream) provide better electrostatic control, reducing leakage and allowing lower VDD. Next-generation gate-all-around (GAA) nanosheet transistors promise even steeper subthreshold slopes (sharper on-off transition), which could allow near-threshold operation at higher speeds. For IoT, this means chips that can run at 0.4 V while still maintaining 100 MHz operation—a game-changer for always-on voice and image processing.

Non-Volatile Logic and Computing in Memory

Emerging non-volatile memories (RRAM, MRAM) can store processor state without a constant power supply, enabling “instant-on” systems that need no state retention flip-flops. Combined with power gating, these can reduce sleep-state leakage to near zero. In-memory computing architectures that process data directly in these memories further eliminate the energy cost of moving data between memory and compute, which dominates many IoT workloads.

Ultra-Low-Voltage SRAM

SRAM remains a major power bottleneck because it typically requires a higher minimum supply than logic (0.7–0.9 V vs. 0.4–0.5 V). New bit-cell designs (e.g., 8T, 10T, and read-disturb-free cells) can operate down to 0.4 V with acceptable yield. The Imec group demonstrated a 0.4 V 28 nm SRAM suitable for IoT applications, showing that the memory wall can be overcome.

Conclusion

Low-power VLSI design is the cornerstone of modern IoT technology. By combining power gating, DVFS, MTCMOS, clock gating, and sub-threshold techniques, engineers can create integrated circuits that operate on microamps of current while still delivering the compute and connectivity required for smart sensing and control. The trade-offs—among leakage, performance, area, and design complexity—are navigated through careful architectural decisions and advanced EDA tools.

Looking ahead, machine-learning-driven power management, novel transistor structures, non-volatile logic, and ultra-low-voltage SRAM will push the boundaries further, enabling IoT devices that are truly energy-autonomous. Designers who master these techniques will drive the next wave of innovation, from smart dust to ubiquitous environmental monitoring. The journey toward ever-lower power continues, and the stakes for a sustainable, connected world have never been higher.

For further reading, see the IEEE survey on low-power VLSI design, the Electronic Design fundamentals article, and the SemiEngineering report on low-power design flows.